{"id":4754,"date":"2020-06-25T10:56:33","date_gmt":"2020-06-25T08:56:33","guid":{"rendered":"https:\/\/deepbluembedded.com\/?p=4754"},"modified":"2024-01-21T00:57:56","modified_gmt":"2024-01-20T22:57:56","slug":"stm32-dma-tutorial-using-direct-memory-access-dma-in-stm32","status":"publish","type":"post","link":"https:\/\/deepbluembedded.com\/stm32-dma-tutorial-using-direct-memory-access-dma-in-stm32\/","title":{"rendered":"STM32 DMA Tutorial – Using Direct Memory Access (DMA) In STM32"},"content":{"rendered":"\n\n\n\n\n
\"Previous<\/a><\/td>\nPrevious Tutorial<\/strong><\/a><\/td>\nTutorial 21<\/span><\/strong><\/span><\/td>\nNext Tutorial<\/strong><\/a><\/td>\n\"Next<\/a><\/td>\n<\/tr>\n
<\/td>\nSTM32 DMA Tutorial – Using Direct Memory Access (DMA) In STM32<\/strong><\/span><\/td>\n<\/td>\n<\/tr>\n
<\/td>\nSTM32 Course Home Page <\/strong><\/span>????<\/a><\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

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In this tutorial, we’ll discuss the direct memory access unit (DMA) in STM32 microcontrollers. We’ll begin with an introduction for what is a DMA unit, when, and why to use it. Afterward, we’ll start discussing the STM32 DMA hardware, its features, and how to configure it in your projects. And some example applications that we’ll be building throughout this course.<\/span><\/p>\n

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\u00a0 \u00a0What Is Direct Memory Access (DMA)?\u00a0 \u00a0<\/span><\/strong><\/span><\/h3>\n

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A Direct Memory Access (DMA) unit is a digital logic element in computer architecture that can be used in conjunction with the main microprocessor on the same chip in order to offload the memory transfer operations. This significantly reduces the CPU load. As the DMA controller can perform memory to memory data transfers as well as peripheral to memory data transfers or vice versa. The existence of DMA with a CPU can accelerate its throughput by orders of magnitude.<\/span><\/p>\n

In no-DMA computer architecture, you’d find it looking something like this shown in the diagram below.<\/span><\/p>\n

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As you can see, the CPU (main processor) has to do all the work of fetching instructions (code) from flash, executing the decoded instructions, and move data to and from peripherals and memory. Imagine having a UART1 data receiver that gets a stream of data that the CPU has to immediately transfer to a local buffer in memory so as not to lose any data packet. This translates into an insane number of interrupts per second being fired by different peripherals like UART, SPI, ADC, etc. And the CPU has to juggle everything and lose more and more time. <\/span><\/p>\n

The fact that switching the context to and from interrupt handlers takes up some cycles that are completely wasted and periodically happens as interrupt signals are getting fired continuously is what makes this architecture problematic to an extent. Having a data stream of 10kB\/s can make a CPU without a DMA be so busy and miss up the timing constraints for the application. The CPU can be seen as if it’s suppressed, and to unleash its full working power this data transfer task has to be handed over to another unit and here it comes the DMA unit to offload these exhausting data transactions from the CPU.<\/span><\/p>\n

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As you can see in the diagram above, the existence of the DMA unit can now direct the data stream coming from the UART peripheral directly to the memory while the CPU doing other stuff and calculations. This parallel cooperation between the CPU and the DMA is where the acceleration stems from.<\/span><\/p>\n

The existence of the DMA unit can sometimes introduce some issues. For example, in an architecture that has a CPU cache when the DMA unit accesses the data memory and writes to a location that is also mirrored in the cache, this will invalidate the data in cache memory. This a challenge to overcome, and there are other but it’ll be a topic for a future article. I just wanted to spot some light on this point, besides being advantageous the DMA can also introduce some issues.<\/span><\/p>\n

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\u00a0 \u00a0STM32 DMA Hardware\u00a0 \u00a0<\/span><\/strong><\/span><\/h3>\n

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For STM32F103C8T6 (The Blue Pill MCU)<\/strong><\/span><\/p>\n

Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations.<\/span><\/p>\n

The two DMA controllers have 12 channels in total (7 for DMA1 and 5 for DMA2), each dedicated to managing memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests.<\/span><\/span><\/p>\n

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The DMA controller performs direct memory transfer by sharing the system bus with the Cortex\u00ae-M3 core. The DMA request may stop the CPU access to the system bus for some bus cycles when the CPU and DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU.<\/span><\/p>\n

The DMA Units In STM32F103 Have The Following Features<\/strong><\/span><\/p>\n